The present invention relates to a method and an apparatus for calibrating an analog-to-digital conversion (hereinafter A/D) apparatus, especially to a method and apparatus for calibrating the phase relationship between clock signals to be applied to a plurality of A/D converters that receive a common analog signal.
It is common to use digital techniques for processing an analog input signal. The analog signal is converted to digital form using an A/D conversion apparatus that samples the analog signal and quantizes it. In order to avoid aliasing, the sampling frequency must be at least twice the frequency of the highest frequency component present in the analog signal. Therefore, in order to enable a high frequency analog signal to be processed using digital technique, it is necessary to employ an A/D conversion apparatus that is responsive to a high sampling frequency. Conventional A/D conversion apparatus that employs a single A/D converter is not able to sample the analog input signal at a sufficiently high frequency for all applications. Therefore, it is conventional for a high speed A/D conversion apparatus to use the so-called interleave technique, wherein the analog input signal is applied to N (integer larger than one) A/D converters and N-phase clock signals are applied to the A/D converters respectively so that the A/D converters operate sequentially. This enables the effective sampling frequency to be increased substantially.
FIG. 1 shows a block diagram of a conventional interleave A/D conversion apparatus. In FIG. 1, the analog input signal is applied through an input terminal 10 to N A/D converters 12 and 14 (in this case, N=2). Each of these A/D converters may be a parallel comparison type A/D converter or a serial-parallel type A/D converter (composed of a parallel comparison type A/D converter, a digital-to-analog converter and a differential amplifier). A clock generator 16 generates two-phase clock signals that are 180 degrees out-of-phase. The A/D converters 12 and 14 convert the analog input signal into two digital signals in response to the two-phase clock signals respectively. Sample and hold circuits or track and hold circuits may be provided as input stages for the A/D converters 12 and 14, or the sampling function may be added to the A/D converters. Since there is a 180 degree phase difference between the clock signals applied to the A/D converters 12 and 14, these A/D converters sample the analog input signal and convert the sampled signal into the digital signals alternately. Thus, the maximum sampling frequency of the A/D conversion apparatus is twice (N= 2) that of each A/D converter.
The digital output signals from the A/D converters 12 and 14 may be directly selected in alternating fashion by a multiplexer. However, in FIG. 1, the output signals from the A/D converters are stored in memories 20 and 22, such as RAMs, respectively. After the storing operation, the contents of the memories 20 and 22 are read and alternately selected by a multiplexer (MUX) 24. The circuit shown in FIG. 1 may be used in a waveform memory apparatus, a transient digitizer, or a digital oscilloscope, for example.
If the A/D conversion apparatus of FIG. 1 samples a ramp waveform 26 (FIG. 2) and executes the A/D conversion operation at a constant period, i.e. at times t.sub.n-1, t.sub.n, t.sub.n+1, t.sub.n+2, the A/D converter 12 samples the ramp waveform 26 and converts the sample values into digital values at the times t.sub.n-1, t.sub.n+1, t.sub.n+3 . . . and the A/D converter 14 samples the ramp waveform 26 and converts the sample values into digital values at the times t.sub.n, t.sub.n+2 . . . as shown in FIG. 2. Under ideal conditions, digital values d.sub.n-1, d.sub.n, d.sub.n+1, d.sub.n+2 . . . will be obtained. However, in practice, the analog input signal is not sampled and converted into digital form at a constant period because of characteristic differences in the characteristics of the A/D converters (e.g., propagation delay time), phase shift errors in the clock signals, differences in propagation delay times of the input stages for the A/D converters, or a combination of these phenomena. These errors have the effect of shifting the times t.sub.n, t.sub.n+2 . . . to times t'.sub.n, t'.sub.n+2 . . . so that the digital values d.sub.n, d.sub.n+2 . . . are shifted to d'.sub.n, d'.sub.n+2 . . . . Thus, the use of multiple A/D converters to accommodate a high frequency input signal introduces errors into the A/D conversion apparatus.
An A/D conversion apparatus architecture for solving the above-described disadvantage, based on the disclosure in U.S. Pat. No. 4,345,241 issued Aug. 17, 1982 and assigned to the assignee of this patent application, is shown in FIG. 3. In this architecture, the A/D converter 12 receives its clock signal through a fixed delay circuit 26, and the A/D converter 14 receives its clock signal through a variable delay circuit 28. The clock signal of the A/D converter 14 leads that of the A/D converter 12 if the delay value of the variable delay circuit 28 is less than that of the fixed delay circuit 26, and the clock signal of the A/D converter 12 leads that of the A/D converter 14 if the delay value of the variable delay circuit 28 is larger than that of the fixed delay circuit 26. In other words, it is possible to adjust selectively the phase differences between the clock signals of the A/D converters 12 and 14.
In order to adjust the phase difference between the clock signals, a ramp generator 32 is selected by a switch 30 so that the ramp waveform signal shown by a solid line 26 in FIG. 2 is applied to both the A/D converters 12 and 14. The A/D converters 12 and 14 alternately convert the ramp waveform signal 26 into digital form and store the converted digital values in the memories 20 and 22 sequentially. After storing a predetermined number of digital values, a control circuit 34, such as a central processing unit (CPU), obtains the digital values d.sub.n-1, d.sub.n+1, d.sub.n+3 . . . from the memory 20 and the digital values d.sub.n, d.sub.n+2, d.sub.n+4 . . . from the memory 22. Then, the control circuit 34 calculates the values d.sub.n -d.sub.n-1, d.sub.n+1 -d.sub.n, d.sub.n+2 -d.sub.n+1, d.sub.n+3 -d.sub.n+2 . . . and adjusts the delay time of the variable delay circuit 28 such that the calculated differences are equal to each other. Thus, the phase difference between the clock signals for the A/D converters 12 and 14 is calibrated.
Therefore, by using the architecture disclosed in U.S. Pat. No. 4,345,241, the conversion error that arises from use of multiple converters can be at least partially eliminated. Hoever, errors may arise due to non-linearity of the ramp waveform if the quantization step of of the A/D converters is small. If the reference signal has a waveform other than a ramp, errors may arise due to deviations between the actual reference waveform and the desired reference waveform. It is very difficult to generate a reference waveform which is sufficiently free of such deviations for calibration of a high accuracy multi-bit A/D conversion apparatus. The architecture disclosed in U.S. Pat. No. 4,345,241, does not enable satisfactory calibration of phase differences of the clock signals for a high accuracy A/D conversion apparatus.